When the counter reaches the fixed count at time period t1, the binary counter resets to 0000 and switches the integrator input to a negative reference voltage –Vref. At the end of the fixed time period t1, the ramp output of integrator is given by The negative ramp continues for a fixed time period t1, which is determined by a count detector for the time period t1. This results in counting up of the binary counter. The output of comparator is positive and the clock is passed through the AND gate. The analog input voltage VA is integrated by the inverting integrator and generates a negative ramp output.
The binary counter is initially reset to 0000 the output of integrator reset to 0V and the input to the ramp generator or integrator is switched to the unknown analog input voltage VA. The logic diagram for the same is shown below.
Hence it is called a s dual slope A to D converter. In dual slope type ADC, the integrator generates two different ramps, one with the known analog input voltage VA and another with a known reference voltage –Vref.
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